Domain-Specific AI Architecture (RISC-V + NPU)
WIOWIZ designs domain-specific architectures combining RISC-V cores with custom neural processing units. We tailor compute, memory hierarchy, and ISA extensions for inference workloads — from edge vision to autonomous systems.
Custom RISC-V Core Integration
Selection, configuration, and integration of RISC-V cores with custom ISA extensions for domain workloads.
NPU Micro-Architecture Design
Systolic arrays, MAC units, activation pipelines, and weight memory designed for target model profiles.
ISA Extension Design
Custom RISC-V instructions for quantized operations, tensor manipulation, and DMA control.
Memory Subsystem Optimization
Scratchpad, cache hierarchy, and DMA design tuned for inference data movement patterns.
Compiler & Toolchain Support
LLVM-based backend support for custom instructions, operator lowering, and model deployment.
Power & Area Optimization
PPA-driven architecture exploration with clock gating, voltage scaling, and datapath sharing.