Scale by adding dies, not by growing one chip
A die-to-die chiplet platform in seven configuration styles, from a CPU-to-memory baseline up to a multi-die AI and HBM mesh. Each style combines WIOWIZ RISC-V and NPU dies over standard interconnects (UCIe, AIB, HBM, CXL and UALink), so systems scale by adding dies instead of growing one large chip.
Architecture
Architectural view. Each block is a WIOWIZ chiplet connected over standard die-to-die links, and internal micro-architecture is not shown.
RISC-V Architecture
WIOWIZ RISC-V compute dies and NPU dies are connected over standard die-to-die links, letting a system scale by adding chiplets (more compute, more memory, more nodes) instead of building one very large monolithic die.
Specifications
| Configuration | Description |
|---|---|
| Config 1 | CPU to on-chip memory, die-to-die baseline |
| Config 2 | CPU to CPU over a real die-to-die PHY |
| Config 3 | CPU to high-bandwidth memory (HBM) |
| Config 4 | AI engine (NPU) to high-bandwidth memory |
| Config 5 | CPU plus NPU with dual HBM |
| Config 6 | CXL memory and I/O expansion |
| Config 7 | multi-node AI and HBM mesh (UALink scale-out with all-reduce) |
| Interconnects | UCIe, AIB, HBM, CXL, UALink |
| Dies | WIOWIZ RISC-V and NPU chiplets |
| IP ownership | WIOWIZ IP and WIOWIZ VIP |
| Design flow | WIOWIZ in-house EDA |
| Status | R&D program (seven configurations in bring-up) |
Key Features
Seven configuration styles
One platform spans a CPU-to-memory baseline up to a multi-die AI and HBM mesh.
Standard die-to-die interconnects
Chiplets talk over open die-to-die standards (UCIe, AIB) rather than a proprietary link.
High-bandwidth memory integration
HBM stacks sit beside compute dies to feed CPU and NPU chiplets at full rate.
CXL memory and I/O expansion
A host interface die adds CXL memory and I/O reach without redesigning the compute dies.
UALink scale-out mesh
UALink ports join nodes into an all-reduce mesh for multi-node AI and HBM.
RISC-V and NPU chiplets
Every compute and AI die is WIOWIZ RISC-V and NPU silicon, architected in house.