Company
The WIOWIZ Story
Company
The tapeout we did not finish
Design & Verification
How do you build trust in an EDA tool with no customer history?
Ideas & Perspectives
Design & Verfication
The Loop Nobody Talks About
EDA & Autonomous
The Game of Imitation: A Way to Build Consciousness
The Silicon Paradoxes
Perspective
The Coverage Paradox
Perspective
The Verification Paradox
Perspective
The Waiver Paradox
Perspective
The Abstraction Paradox
Perspective
The Automation Paradox
WIOWIZ EDA Platform
WIOWIZ EDA Platform Series
One RTL design, different verification questions
WIOWIZ EDA Platform Series
Reading an EDA log instead of looking for PASS
WIOWIZ EDA Platform Series
Inside a Truti CDC/RDC Audit
WIOWIZ EDA Platform Series
Inside a Hetu-Formal Run
WIOWIZ EDA Platform Series
What Vajra-LP Checks
FSiMX Engine
FSiMX Engine Series
Why FSimX Built Its Own SystemVerilog Front End
FSiMX Engine Series
What Does Two-State Simulation Hide?
FSiMX Engine Series
An Assertion That Wasn’t Evaluated Did Not Pass
FSiMX Engine Series
How FSimX Decides When Compiled Execution Is Safe
FSiMX Engine Series
How Fast Can a Simulator Turn RTL Into a Runnable SoC?
EDA & Autonomous
FSiMX: Building a Verification Simulator as a Platform
FSiMX Studio
FSiMX Studio Series
RTL Simulation, Debug and Coverage in One Window
FSiMX Studio Series
RISC-V HW/SW Co-Simulation Debug
FSiMX Studio Series
Drag-and-Drop Signals, Trace a Driver to Source
FSiMX Studio Series
Protocol Transaction and Memory Viewers
FSiMX Studio Series
Every Coverage Metric in One Database
FSiMX Studio Series
Formal Reachability and UNR Closure
FSiMX Studio Series
Power-Aware Coverage from UPF Intent
Verification
EDA & Autonomous
EQWAVE: Timestamps lie. Behavior doesn’t
EDA & Autonomous
Bridging Digital and Photonic Verification
SoC Virtual Platform
SOCVP Series
Boot a complete SoC from one binary
SOCVP Series
Three RISC-V cores, one boot, one fabric
SOCVP Series
The Catalogue Runs
SOCVP Series
Architecture is not a directory listing
SOCVP Series
Compose. Boot. Repeat.
SoC Reference Designs
Reference SoC
WZ-HFT: Market data to order in 12 cycles
AI Silicon & Inference
EDA & Autonomous
VAIDAS: Real-Time ADAS Inference on VAI Architecture
EDA & Autonomous
VAI (Virtual AI Inference): What Hardware Engineers See
EDA & Autonomous
VAI (Virtual AI Inference) to Mini-GPT : RTL-Verified Transformer Execution on WZ-NPU
Physical Design & Signoff
Chiplets & Memory
EDA & Autonomous
Chiplets, Made Practical: A UCIe™ D2D reference implementation for students and startups
Analog & Custom (WZ-SPICE)
WZ-SPICE Engine Series
WIOWIZ Native SPICE: What Our Analog Simulator Runs Today
WZ-SPICE Engine Series
WIOWIZ uPHY: Coupling FSimX and Native SPICE on a 2.5 Gb/s Recovered-Clock Link
WZ-SPICE Engine Series