WIOWIZ Native SPICE at Scale: An 8T SRAM Compute Macro to 170,240 MOS Devices

Circuit simulators often change character as the matrix grows. We ran WZ-SPICE on a tiled SG13G2 SRAM compute-in-memory macro at increasing sizes, with ngspice and Xyce running the same size-specific netlists as references. The block is a regular array rather than a diverse analog design. The completed sweep reaches 170,240 expanded MOS devices.

What the WIOWIZ CIM hierarchy contains

The source block is a WIOWIZ 16 by 16 compute-in-memory tile in IHP SG13G2. One tile contains 256 8T SRAM cells, 16 three-device write-precharge circuits, and 16 read-precharge devices. Flattened for simulation, that is 2,128 MOS devices per tile.

WIOWIZ CIM tile and scale hierarchy

Larger points repeat that designed tile while sharing global row and column nets. No synthetic transistor mesh is added. The completed 128 by 160 macro is an 8 by 10 tile grid: 80 tiles, 20,480 SRAM cells, and 170,240 MOS devices.

Every SRAM cell is preloaded to one. The 10 ns transient then applies a 0.4 V row activation and exercises the transistor read and compute path. This sweep measures that preloaded compute operation; it does not include write-cycle timing.

Memory

The clearest result is memory. At every completed overnight size, WZ-SPICE used less peak RSS than both references. MiB values are rounded for display; the retained KiB values are exact.

Across the six completed overnight points, WZ-SPICE reported zero dense fallbacks. The factor fill ratio stayed between 1.141 and 1.142. Full values remain in the dataset.

Runtime

The trade-off is wall time.

At 170,240 devices WZ-SPICE took 12,098.00 seconds, compared with 971.48 seconds for ngspice and 602.03 seconds for Xyce. Across the completed overnight points it was 16.24 to 32.07 times slower than the fastest retained reference. The profiling evidence identifies model evaluation as a substantial cost. Parsing, residual evaluation, numeric factorization, and iteration control also contribute to the full wall time.

What was checked

The retained answer comparison is one node, rbl0, sampled at 5 ns. From 12,768 devices upward, the largest retained absolute difference is 2.23 microvolts against ngspice and 1.13 microvolts against Xyce. This is not a waveform-wide maximum. The 2,128, 4,256, and 8,512-device points retain runtime and memory but no voltage-difference number, so they are performance-only points.

A 255,360-device array was attempted. WZ-SPICE stopped at the 14,400-second limit with peak RSS 561,304 KiB, or 548.15 MiB. ngspice and Xyce were not run at that size. It is neither a completion result nor a cross-engine comparison.

The exact size-specific netlists and run records are retained with the study. The compared solver build identities are incomplete, so this study is not described as fully reproducible. The memory result is the present strength. Runtime is the open optimization problem, and both remain visible in the same table.

Scope

These are execution, memory, sparse-health, and single-sample voltage measurements on one regular tiled SRAM compute-in-memory macro. Memory and runtime are retained across the completed sweep. Voltage agreement is limited to rbl0 at 5 ns from 12,768 devices upward. This is not waveform-wide validation, silicon correlation, or tapeout qualification.