WIOWIZ Native SPICE: What Our Analog Simulator Runs Today

We are not building SPICE as an isolated waveform generator. We are building the analog execution layer of the WIOWIZ verification platform.

Why an owned analog engine

A mixed-signal SoC is not purely digital with an analog appendix. Configuration, calibration, protocol control, interrupts, scoreboards, and coverage live in the digital verification environment. Continuous-time behavior lives in transmitters, receivers, data converters, oscillators, sensors, supplies, and clock-recovery loops. Verification loses the system interaction when those two sides run as unrelated jobs.

ngspice and Xyce are mature circuit simulators and valuable independent references for this work. We are not building WIOWIZ Native SPICE because those projects are inadequate, and we do not frame our engine as their replacement. We use them as external, file-based references where a comparison helps us test a specific result.

The reason for an owned engine is architectural. FSimX must be able to ask the analog solver to attempt a timestep, inspect a threshold crossing, roll back, settle digital and analog feedback at the same simulation time, and commit only an accepted state. The same session must expose results to scoreboards, assertions, coverage, diagnostics, and replay. That requires control of the analog state machine, not only access to a finished waveform.

The established mathematics we build on

The numerical foundations of circuit simulation are established engineering methods. Modified nodal analysis, Newton iteration, sparse factorization, continuation, and implicit time integration are not WIOWIZ inventions. Our work is to implement and own those stages, connect them through explicit contracts, preserve deterministic accepted state, and integrate them with the verification flow.

That table is the distinction we want to make. The mathematics belongs to the circuit-simulation field. The implementation, state ownership, diagnostics, and verification integration are the WIOWIZ engineering surface.

Capability and qualification are tracked separately. In this article, implemented means the code path exists in the native engine. Exercised means it has run in a named, bounded fixture. Numerically compared means a retained result was checked against an independent reference under a stated contract. Accuracy-qualified requires the relevant model and analysis to pass its authorized comparison campaign. Roadmap means direction, not a current capability.

What WIOWIZ owns in every solver stage

The frontend parses SPICE syntax, resolves hierarchy and models, builds the circuit IR, and constructs the requested analysis. Unsupported syntax must fail explicitly rather than disappearing as a comment. Native devices and admitted compiled models enter the same matrix-independent evaluation boundary.

Devices stamp currents, charges, and derivatives into a modified nodal analysis system. R, C, L, independent sources, E/F/G/H controlled sources, mutual inductance, bounded switches, diode, MOS1, and the clean-room BSIM3 path form the native device core. Voltage-defined elements add branch-current unknowns and equations. Nonlinear devices contribute terminal residuals and Jacobians at the current Newton state.

Sparse assembly separates topology from changing numeric values. Fill-reducing ordering and symbolic analysis establish the factor structure once for a fixed graph; the symbolic result is cached and reused while Newton states and accepted timesteps change. Numeric refactorization works on that structure. In the completed tiled-SRAM scale sweep, the factor fill ratio stays near 1.14 and dense fallback remains zero through 170,240 MOS devices.

The nonlinear engine evaluates the physical residual, solves for a Newton update, applies convergence checks, and advances through a fixed recovery ladder when necessary: improved initial guess, device limiting, Newton damping, matrix scaling, source stepping, GMIN stepping, and pseudo-transient continuation. Recovery does not waive numerical acceptance.

Transient analysis keeps candidate state separate from immutable accepted history. Backward Euler is the conservative default; trapezoidal and variable-step BDF2 are also implemented with bounded LTE control, source breakpoints, rejected-step rollback, and bounded trapezoid-to-BDF2 ringing suppression. A rejected trial cannot publish model state or events.

WIOWIZ Native SPICE engine architecture

The analysis layer includes native OP, DC, AC, transient, transfer, and pole-zero paths, with bounded noise, sensitivity, distortion, S-parameter, HB, PSS, PAC/PXF, and PNOISE foundations at different qualification depths. RF execution is real; broad authorized RF accuracy is still in progress.

The model path is also owned. Verilog-A source passes through WIOWIZ preprocessing, lexer, parser, source-located AST, semantic checks, deterministic IR, and forward automatic differentiation for analytic current, charge, and Jacobian terms on the supported surface. Build-time emission produces modules admitted through signed ABI v2 through v10 contracts. Compilation is not treated as accuracy qualification: PSP103T has bounded electrothermal engineering execution, HICUM has bounded intake without a foundry card or accuracy claim, and BSIM-CMG remains compiler-census only.

Why analog rollback changes AMS architecture

Consider an analog trial from 10.0 ns to 10.5 ns. A comparator threshold is crossed at 10.31 ns. Treating the analog engine as a command-line waveform producer is insufficient because the crossing may change digital control, which may immediately change an analog DAC or switch.

The coupled coordinator performs this sequence:

1. Propose the analog trial from 10.0 ns to 10.5 ns.
2. Detect and interpolate the comparator crossing at 10.31 ns.
3. Reject the original 10.5 ns candidate state.
4. Roll the analog solver back to the last accepted state.
5. Advance precisely to the 10.31 ns crossing boundary.
6. Schedule the corresponding digital event in FSimX.
7. Drain every deterministic same-time delta cycle.
8. Apply resulting DAC, held-source, switch, or control changes to the analog partition.
9. Re-solve the same boundary until analog and digital feedback settles, then commit the accepted state.
10. Continue toward the next digital event or analog trial limit.

The product-native AMS kernel uses four-state scalar and bus events ordered by (time, delta, sequence). It provides explicit resolved wires, transport and inertial delay, bounded combinational and sequential primitives, timing monitors, flash encoders, SAR controllers, and typed comparator, DAC, sample-and-hold, and resistor-switch bindings. Event, delta, crossing, boundary, and feedback-iteration limits fail closed.

FSimX and Native SPICE in one verification session

FSimX owns SystemVerilog scheduling, digital control, protocol behavior, and the verification environment. WIOWIZ Native SPICE owns the transistor partition, nonlinear solve, integration history, and analog crossing detection. The fsx-ams-2 boundary makes D2A controls, A2D observations, analog trials, rollback, accepted-state commit, and same-time settlement explicit.

The recovered-clock uPHY is the current concrete example. FSimX generates alternating training and PRBS-7 traffic, applies bounded coarse-frequency control, and scores recovered data. Eight digital-to-analog controls drive a 172-MOS-device transistor TX, channel, receiver, and clock-recovery path. Four observations return recovered clock, recovered data, loop-control voltage, and charge-pump state. Two coupled replicas produce byte-identical analog and digital records across a 120 ns run.

This is why owning both engines matters to us. A digital event can be traced through the boundary, analog solve, threshold decision, returned event, and scoreboard outcome without handing accepted-state ownership to an opaque orchestration layer.

From transistor decisions to UVM scoreboards

The target architecture is selected transistor-level analog partitions inside an otherwise digital SoC verification run. It is not transistor-level SPICE simulation of every device in a full SoC.

WIOWIZ SoC mixed-signal verification flow

The intended flow is:

1. A UVM sequence programs digital configuration registers and starts a transaction.
2. RTL control, protocol, DMA, interrupts, and firmware-visible state execute in FSimX.
3. Selected PHY, ADC, PLL, sensor, or power blocks cross into WIOWIZ Native SPICE at explicit D2A boundaries.
4. Transistor-level analog state produces clock, comparator, lock, data, or monitor decisions.
5. A2D boundaries return those decisions to RTL at deterministic event times.
6. UVM scoreboards, assertions, functional coverage, and protocol checks observe the complete system behavior.

A future example could configure a PHY through its RTL register interface, send packets through the digital datapath, cross into a transistor TX/channel/RX/CDR partition, return recovered bits and clock to RTL, and score the transaction in UVM. That is the direction. The current evidence is a bounded uPHY demonstrator and bounded ideal closed-loop AMS fixtures, not full-SoC mixed-signal qualification.

What the current numbers demonstrate

The numbers span solver behavior, mixed-signal coordination, and circuit scale:

The memory result is the clearest current scale strength. The runtime gap is equally real. The uPHY result demonstrates deterministic coupling and system interaction, not cross-engine parity. The SAR result demonstrates the controller and ideal closed loop, not a transistor converter.

What still has to improve

The next engineering work is specific:

1. Reduce model-evaluation runtime without sacrificing sparse memory behavior, accepted-state correctness, or deterministic replay.
2. Broaden adaptive timestep, LTE weighting, and integration-method policy on real mixed-domain workloads.
3. Extend structured diagnostics across more real circuit failures and validate solution-memory remedies on distinct real decks.
4. Move compact models from compiler intake to signed execution and authorized ModelQA accuracy comparison.
5. Repair and requalify the open RF S-parameter discrepancy before making a public RF accuracy claim.
6. Extend AMS from ideal boundaries and one uPHY path to transistor-level ADC, PLL, PHY, sensor, and power partitions.
7. Add broader timing, nonlinear same-time feedback, analog settling, charge storage, wider RTL structures, and stronger mixed-signal negative controls.
8. Connect analog outcomes more directly to UVM scoreboards, assertions, coverage, and replay artifacts.
9. Add silicon correlation only when measured data, licensed models, corners, and a frozen comparison contract are available.

Roadmap to SoC-level mixed-signal verification

The roadmap is to make analog simulation a selectable verification partition, not a separate downstream activity. A verification engineer should be able to keep the SoC, software-visible control, and UVM environment in FSimX while choosing which analog-critical blocks execute at transistor level in WIOWIZ Native SPICE.

The progression is staged: maintain the bounded uPHY evidence; close core solver and model gaps; qualify authorized compact models; extend comparator, DAC, sample-and-hold, switch, timing, and analog-settling behavior; qualify transistor ADC and PLL loops; connect their outcomes to full digital scoreboards and coverage; then expand to selected analog partitions in larger SoC verification environments.

We are building toward that flow. We have not completed it. The realistic objective is a full-SoC digital verification session with selected transistor-level analog partitions, not an impractical promise to solve an entire SoC transistor netlist in SPICE.

Scope

WIOWIZ Native SPICE is a working native engine with owned circuit formulation, sparse solving, nonlinear recovery, analyses, model compilation, diagnostics, and a bounded AMS kernel. Numerical comparison in the frozen five-case core set currently passes the named AC and pole-zero cases; hierarchical subcircuit parsing, sensitivity syntax, and VBIC coverage remain gaps in that campaign. Broad RF accuracy is open, and the held LNA result is not used here. AMS evidence is limited to named ideal fixtures and the recovered-clock demonstrator. The scale study is memory-strong and runtime-slow, with its voltage comparison limited to rbl0 at 5 ns. SoC-level mixed-signal verification is a roadmap direction, not a completed qualification. This is not silicon correlation or tapeout qualification.