WIOWIZ uPHY: Coupling FSimX and Native SPICE on a 2.5 Gb/s Recovered-Clock Link

A serial-link PHY does not fit cleanly on one side of the analog-digital boundary. The transmitter, channel, receiver front end, and clock-recovery loop contain continuous-time device behavior. Training, bounded frequency control, and recovered-data scoring are digital. WZ-SPICE is our native analog simulator and FSIMX is our digital simulator. In this experiment FSIMX drives eight digital-to-analog boundary ports into a WZ-SPICE device-level transmitter, lumped differential channel, receiver, and recovered-clock CDR. Four analog-to-digital and monitor ports return recovered clock, data, control voltage, and charge-pump state to FSIMX.

The uPHY architecture in this run

This is the WIOWIZ uPHY recovered-clock demonstrator at 2.5 Gb/s, 1.2 V, and 27 C. FSIMX generates a 64-bit alternating training sequence followed by PRBS-7 traffic. It also owns bounded coarse-frequency control and the recovered-data scoreboard. Eight controls cross into the transistor simulation: data, TX clock, enable, three feed-forward-equalizer controls, and coarse UP and DOWN commands.

WIOWIZ uPHY mixed-signal architecture

The analog path contains 172 MOS devices in the retained standalone replay. It starts with the transistor transmitter and its feed-forward-equalizer controls, then crosses a lumped differential channel with 50 ohms in series and 1.5 pF to ground on each leg. The receiver uses a continuous-time linear equalizer and StrongARM sampling. Clock recovery closes through a three-sample Alexander bang-bang phase detector, matched 25 microampere charge-pump path, loop filter, and ring VCO. Recovered clock, recovered data, loop-control voltage, and charge-pump state return to FSIMX.

Deterministic coupled execution

Two coupled endpoint replicas each exited zero and scored 49 of 49 payload edges with zero scoreboard errors. Their 1,415-row analog waveforms are byte-identical, as are their 64-event digital traces. The one-way coarse-to-fine handoff occurred at 70.01 ns. No fitting was performed.

The same bounded digital-analog experiment therefore produces the same retained analog waveform and digital event trace.

Independent standalone replays

The frozen FSIMX control trace was then replayed through the same 172-device circuit in three standalone analog engines. The table is an engineering comparison, not a parity table. Display values are rounded.

Recovered-period comparison

CTLE own-edge engineering metrics

None of the last ten recovered periods from any engine stays inside the retained 380 to 420 ps band for every edge. The engines recover different periods and phases. Each CTLE differential is therefore measured at that engine's own recovered rising edge. The horizontal metric is twice the distance to the nearest CTLE zero crossing. It is not a statistical BER eye contour.

Why ngspice reports 46 of 49

The frozen sequence oracle samples ngspice data_out 200 ps after the coupled WZ-SPICE recovered-edge timestamps. Under that foreign-clock convention it reports 46 of 49, with differences at zero-based indices 9, 12, and 22. The nearest ngspice edges arrive 148.01 ps, 53.66 ps, and 111.85 ps later. On the unchanged waveform, sampling 200 ps after ngspice's own nearest recovered edge produces the expected 0, 0, and 1 for those three bits. No waveform was rerun, no alignment was tuned, and no fitting was performed.

Bit 22 foreign-clock sampling explanation

This explains the three retained disagreements as foreign recovered-clock sampling. It does not erase the original 46/49 result, establish waveform parity, or create a universal symbol mapping between clocks with different edge counts.

Reproducing the comparison

The WZ-SPICE and ngspice replay retains the exact simulator builds, decks, control replay, and output waveforms used for the comparison. This specific two-engine standalone replay is fully reproducible from those records.

The Xyce output waveform is retained, but its executable identity is not. We therefore do not describe the full three-engine comparison as independently reproducible. Tool-specific decision-output voltage is also excluded: WZ-SPICE and ngspice expose held latch outputs, while the retained Xyce topology exposes internal StrongARM regeneration nodes.

Owning the digital engine, analog solver, and explicit boundary makes the coupled run inspectable as one chain. The claims here still stop at what that run records.

Scope

This is a bounded 120 ns, one-corner recovered-clock demonstrator with 49 scored payload bits. It uses a local SG13G2-like BSIM3 wrapper rather than the official IHP PSP or foundry card, a UIC-precharged VCO, a lumped channel, and a non-clocked TX FFE approximation. Cold-start acquisition, BER, PVT, jitter tolerance, silicon correlation, protocol-PHY qualification, and cross-simulator parity are not established. The external runs replay frozen FSIMX decisions and are not independent controller oracles.