The claim is small enough to state in one line: run one command and a complete WIOWIZ SoC boots, executes its firmware, and checks its own answer. The rest of this article is that claim shown, and then named.
The boot is the demo
The AI Edge system is a RISC-V control core sitting beside DMA, a CNN accelerator, an NPU and pooling engines on one shared bus. The firmware does not poke isolated registers for a screenshot. It runs one inference end to end and checks the answer:
$ bin/socvp boot ai-edge
WIOWIZ AI-EDGE E2E: one input tensor, one journey, checked at the end
E2E: dma ifmap -> cnn conv -> npu gemm -> spool reduce
E2E stage1 dma0 : input tensor RAM -> cnn0 ifmap (108 B) DONE
E2E stage2 cnn0 : conv3x3 3ch 6x6 -> 8ch 4x4 DONE
E2E stage3 dma0 : requantized fmap RAM -> npu0 ga (128 B) DONE
E2E stage4 npu0 : gemm 16x8 * 8x8 DONE
E2E stage5 spool0: sumpool2x2 8ch 4x4 -> 8ch 2x2 DONE
E2E check: 32/32 match the build-time oracle
AI_EDGE_E2E: PASS
Five engines, one tensor, and the result compared element for element against a reference computed when the firmware was built. All 32 outputs match. The platform then prints its own counters for the run:
[VP] result : PASS
[VP] instructions: 16966
[VP] bus txns : 25353
[VP] uart bytes : 1228
[VP] illegal insn: 0
[VP] decode errs : 0
16,966 instructions retired and 25,353 bus transactions moved to carry that one inference through five engines. Those numbers are the receipt: the work happened, it happened over the system address map, and the output was checked against the reference.
A green you can trust
A model is only worth as much as the faults it catches. Two of the counters above exist to catch the failure mode where a demo prints PASS while quietly executing garbage.
illegal insn: 0 means every instruction the firmware executed was legal for the core it ran on. The AI Edge core is rv32im. An instruction from an extension it does not implement, an atomic or a double-precision float, is not silently ignored. It is rejected, and a boot that executes one fails. A success flag written afterwards cannot override a fault that already stopped the run.
decode errs: 0 means no instruction word failed to decode. Together these turn the PASS from a message the firmware chose to print into a claim the platform is willing to stand behind. This is the whole reason the counters are on screen and not buried in a log.
Watch the same run in Studio
The terminal boot and the graphical cockpit are the same execution, not two builds. Open Studio on the same system and you are looking at the state the boot above produced: the program counter, all 32 architectural registers with their post-run values, the bus transactions that actually flowed, and the topology the firmware drove.
HALTED retired=16966 with the 32/32 end-to-end check — the same numbers the terminal reported.Run advances continuously, Pause stops on the current instruction, and Step moves one instruction at a time. Reads land on RAM, writes land on the UART, and the DMA traffic between the accelerators is visible as it happens. Every value in the panels came from the boot.
What you did not need
Everything in the panels you just saw — the boot, the checked result and the live Studio state — happened without a simulator licence, a compiler on the host, or a verification environment to set up. That is what we call the Zero EDA experience.
Zero EDA is less a claim than a goal we are working toward. A simulator seat is out of reach for a lot of students and small teams, and that cost is often the reason a good engineer never gets to try a piece of silicon before committing to it. If evaluating an SoC costs nothing but a command, more of them can. Today that means WIOWIZ IP. The direction we want to take socvp is the same easy boot for a design you bring yourself, so that trying an idea keeps getting simpler rather than harder.
Run it ten times, diff nothing
The boot is deterministic. The same package on the same input produces the same instruction count, the same bus transaction count and the same output, byte for byte, every time. That is a property of how the package is built as much as how it runs: the shipped archive has a published SHA-256, and it verifies its own installed files before it will execute.
$ bin/socvp check
socvp: package integrity verified
A model whose numbers wander between runs cannot be used as a reference. This one does not wander, which is what lets 32/32 and 16,966 be quoted as facts rather than as one lucky run.
What it is, and what it is not
socvp is a functional model. It is not an RTL simulator and it is not cycle-accurate, so the instruction and transaction counts above are work actually executed, not a timing claim. It does not import your RTL; it runs WIOWIZ IP that WIOWIZ packaged. The value it trades for those limits is speed and a boundary it states out loud: a complete SoC that boots in one command, checks its own result, and names the faults it catches.
The rest of this series stays with what runs today. You will explore three different RISC-V cores on one fabric, qualify a catalogue whose entries actually run, open the architecture of a chip as a navigable tree, and compose a new SoC of your own from the same parts. Each one is a command you can run and a result you can check.
Download socvp
socvp is available now. It ships as a Docker bundle from the WIOWIZ website — download it, build the image, and run the same boot you just read about.
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