A datacenter Data Processing Unit that offloads the host
The DPU is a datacenter Data Processing Unit that offloads networking, storage and data movement away from host servers, freeing CPU cores for application work. It is built on RISC-V with hardware packet processing, high-bandwidth memory and a chiplet-ready interconnect, and it targets SmartNIC and datacenter scale-out workloads. This page describes an architecture direction in development, not a shipped product.
Architecture
Clean architectural view of an in-development direction. Every block is WIOWIZ IP on our own RISC-V control cluster, and internal micro-architecture is not shown.
Specifications
| Category | Datacenter Data Processing Unit (SmartNIC class) |
|---|---|
| Control CPU | RISC-V control cluster |
| Datapath | Hardware packet processing, DMA data mover |
| Memory | High-bandwidth memory (HBM) controller |
| Host interface | PCIe and CXL |
| Network | Ultra Ethernet |
| Accelerators | Crypto and compression (optional) |
| Scale-out | Chiplet-ready (die-to-die) |
| IP ownership | WIOWIZ IP and WIOWIZ VIP |
| Design flow | WIOWIZ in-house EDA |
| Status | Architecture, in development |
RISC-V Architecture
A RISC-V control cluster runs the control plane and management while hardware datapaths handle packet processing and data movement at line rate. The design is built for chiplet scale-out with high-bandwidth memory, keeping the control and orchestration in software and the heavy per-packet work in dedicated silicon. It is WIOWIZ IP, architected and verified with our in-house EDA from spec to sign-off.
Key Features
Hardware packet processing
Parse, classify, match and steer packets in dedicated silicon at line rate, off the host CPU.
RISC-V control plane
A RISC-V control cluster runs management and orchestration while datapaths move the data.
High-bandwidth memory
An HBM controller feeds buffers and lookup tables for demanding networking and storage flows.
PCIe and CXL host interface
Connects to host servers over PCIe and CXL for coherent, low-overhead data movement.
Chiplet-ready scale-out
A die-to-die interconnect targets datacenter scale-out across a chiplet-ready design.
WIOWIZ IP and VIP
Fully WIOWIZ IP, architected, implemented and verified with WIOWIZ EDA.