Functional coverage says the logic was exercised.
It does not say the power intent was.
Power-aware coverage measures whether the domains powered down, isolated, retained, restored and woke correctly.
A low-power design carries intent that ordinary coverage never sees. The UPF describes power domains, isolation, retention, and the legal power states. A functional coverage report can read 95 percent while not one domain was ever powered down in simulation. The states that matter most, the ones that only exist because the chip saves power, sit outside the code and functional metrics entirely.
Power-aware coverage is a separate model that measures that closure. It is gated on its own and is never averaged into the code or functional number, because blending a power metric into a code average is how a design signs off with its power sequencing untested. It takes two inputs: a UPF-derived inventory as the denominator, and the simulator's runtime event stream as the hits. Coverage bins the events the design actually produced against the intent the UPF declared.
The measurement model: inventory and events
The inventory is authored upstream from the UPF, one entry per power point with a stable identifier, so a run compares against a fixed denominator rather than against whatever happened to occur. The event stream is what FSiMX observed while the design ran: a domain entering a state, an isolation applied and released, a retention save followed by a restore. Coverage joins the two. A power point with no matching event is uncovered, and the report says so by name.
The power parameters it measures
Each parameter below is a first-class collector, ingested and gated on its own terms:
| Collector | What it measures | Counted covered when |
|---|---|---|
| Domain state | per-domain ON, OFF, RETENTION and related states | that state was entered |
| PST state | named power-state-table states, with a per-domain vector (the state-by-domain matrix) | the state was entered |
| PST transition | legal transitions, and illegal ones as negative controls | legal: the transition was taken; illegal: attempted and detected |
| Isolation | isolation strategy per domain crossing | apply and release both seen |
| Retention | retention group | a save with a matching restore |
| X-propagation | corruption containment across an off domain | injected and contained; any escape is a defect |
| Recovery | functional wake | a domain resumed after an off |
| DVFS point | operating points, with voltage and frequency when the producer emits them | the operating point was entered |
| DVFS transition | moves between operating points | the move was taken; frequency raised before voltage is good is a defect |
| Structural | domains, switches and level shifters from static low-power signoff | recorded as context, not counted as simulation coverage |
Negative controls, and the false-green it refuses
Two mechanisms keep the metric from reading better than the design behaved. An illegal transition is a negative control: it counts only when it was attempted and detected, never as an ordinary hit, and an illegal edge taken without detection is reported as a defect rather than as coverage. Scenario correlation catches the classic false-green, a power scenario that was requested while no power-down or retention state was ever entered. The mini SoC feed in this release shows exactly that case rather than hiding it, because the test did not drive a power-down yet.
The residual is gated, never rounded to a comforting number. A run reports one of a small set of verdicts:
PASS_POWER_AWARE_FUNCTIONAL POWER_COVERAGE_INCOMPLETE: STATE 2/4 ... POWER_COVERAGE_DEFECT
Where LPG, SPG and APG fit
Power-aware design classifies its supply and ground nets, and three of those classes carry names an implementation engineer will recognize:
- LPG, Local Power Ground: the supply tied to a specific local logic block or power domain, the domain that gets scaled or shut down.
- SPG, Switched Power Ground: a net routed through header or footer power-switch transistors, connected and disconnected as a domain enters and leaves sleep.
- APG, Always-On Power Ground: an unswitched, permanent net for the cells that must never lose power during a power-down, the retention flip-flops, the isolation clamps, and the controllers that sequence the wake.
These are generic engineering nomenclature from the physical-implementation and power-aware flows, popularized by the EDA toolchains; they are not reserved keywords in IEEE 1801, which expresses the same intent through generic supply-net and power-state constructs. That distinction is why coverage stays class-agnostic: it bins events against whatever classes a methodology declares, so LPG, SPG, APG and DVFS closure all flow through the same collectors. The always-on class is where isolation and retention coverage carry the most weight, because those are exactly the cells a power-down must not corrupt.
What is built, and what completes later
The measurement model is built. Every parameter above is ingested and gated, with negative-control and defect semantics, false-green detection, gated closure, and a drill-down GUI with the state-by-domain matrix, the transition matrix, per-collector boards, and scenario correlation. It is demonstrated on a PCIe run with IP-agent vectors and on wz_mini_soc with an inline power feed.
What remains is content and depth as the SoC gains power strategies, which is gated on the producers rather than on coverage:
- Driven power runs that power domains down, so the collectors show hits instead of a false-green.
- The SoC-level state table, the integrated per-domain vectors from the full-chip UPF rather than per-IP.
- The step timeline, observed against required transition sub-steps: quiesce, clock-stop, retain, isolate, off, power-good.
- DVFS voltage and frequency values and unsafe-ordering defects, once the engine carries a voltage and frequency model.
- Power source anchors, so a power point double-click reaches its UPF or RTL declaration.
- Per-class closure for LPG, SPG, APG and DVFS once the scenarios that drive those domains are mapped onto the SoC.
Coverage measures closure. It does not author the power intent or define the classes, and separating those jobs is what keeps the metric from marking its own work.
Power-aware coverage says the design saved power the way its intent required.
Download FSiMX Studio
FSiMX Studio is available now. It ships as a Docker bundle from the WIOWIZ website — download it, build the image, and run the same examples, waveforms and coverage you saw in this article. The native FSiMX engine, vWIZ-Wave and vWIZ-Coverage, in one window.
Download FSiMX Studio on wiowiz.ai →
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